A new DCache prefetch algorithm based on branch prediction information for AI industrial engineering

This work proposes a novel cache prefetching algorithm and corresponding microarchitecture for high-performance Central Processing Unit (CPU) designs. Existing stride-based and conventional DCache prefetching schemes have limited prediction accuracy for loop-intensive workloads, fail to fully exploit branch prediction metadata, and easily induce cache pollution and unnecessary memory bandwidth and power consumption—these constitute the key research gaps addressed in this work. This study aims to leverage branch prediction information to optimize DCache prefetching, accurately identify program loop structures, and reduce cache miss rates while avoiding excessive redundant prefetch operations. The research methodology adopts the Gem5 simulation platform to conduct comparative experiments across typical workloads; we design a dedicated branch history table (BHT) replacement strategy with repetition and usage counters, define clear update rules and loop detection thresholds, and adopt statistical analysis, including confidence intervals, variance and significance testing, to evaluate performance. Quantitative experimental results show that the proposed scheme effectively reduces the DCache miss rate by 2.443%, achieves stable Instructions Per Cycle (IPC) performance by 0.4716 instructions per cycle with negligible overhead, and significantly reduces unnecessary data prefetching, cache pollution and power cost compared with traditional stride prefetching. The optimized design is well-suited for general-purpose CPU scenarios as well as AI training and inference workloads dominated by loop-parallel computation, offering a lightweight and high-performance alternative to existing data prefetching approaches.