Elia Mateu-Barriendos, Alvaro Gómez-Pau
Artificial neural networks rely on vector–matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10×1 SNN implemented in a 130 nm CMOS technology validate the proposed architecture, while application to a trained 64×10 SNN for digit classification further demonstrates its feasibility for SNN inference.
@article{05b0c842-63c4-423a-acdb-a5a0ac9598b7,
title={2026 MateuBarriendos Analog Memristive SNN Readout},
author={Elia Mateu-Barriendos and Alvaro Gómez-Pau},
year={2026},
language={en}
}TY - JOUR TI - 2026 MateuBarriendos Analog Memristive SNN Readout AU - Elia Mateu-Barriendos AU - Alvaro Gómez-Pau PY - 2026 LA - en ER -
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