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Zero-Instruction Sensor Reads: Register-Mapped Peripherals and Hardware PWM on a Five-Stage Soft Processor

Nathanael Ren

2016ensoft processorFPGAhardware designembedded systems

Abstract

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We present a case study in application-driven specialization of a five-stage soft processor, evaluated on the inner control loop of a reaction-wheel self-balancing bicycle. Starting from a custom 32-bit RISC core in the MIPS tradition—five pipeline stages, full operand forwarding with a single-cycle load-use interlock, and a 33.33 MHz clock on an Artix-7 FPGA—we specialize the design in two ways. First, two frequently accessed peripheral inputs are mapped directly into architectural register state, allowing for continuous updates by hardware. Second, four periodic pulse-width-modulation (PWM) channels are offloaded to hardware, reducing software overhead. Thus, all ten sensor reads in the control loop incur no dedicated instruction cost, which contrasts with the memory-mapped equivalent that requires explicit loads, leading to significantly reduced instruction counts and cycles. We analyze two configurations: the archived one with a worst-case loop of 91 cycles and the integrated one with a loop of 43 cycles. These configurations demonstrate margins of over 7,000× against a 20 ms actuation frame, underscoring the benefits of our design in terms of instruction efficiency and software simplicity. The contribution includes a detailed assessment of the implications of these design choices on performance and operational characteristics.

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Cite This Work

@article{0de0d7c1-8e89-48da-ae7c-c8f33a5e361b,
  title={Zero-Instruction Sensor Reads: Register-Mapped Peripherals and Hardware PWM on a Five-Stage Soft Processor},
  author={Nathanael Ren},
  year={2016},
  language={en}
}
TY  - JOUR
TI  - Zero-Instruction Sensor Reads: Register-Mapped Peripherals and Hardware PWM on a Five-Stage Soft Processor
AU  - Nathanael Ren
PY  - 2016
LA  - en
ER  -

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