Zero-Instruction Sensor Reads: Register-Mapped Peripherals and Hardware PWM on a Five-Stage Soft Processor

We present a case study in application-driven specialization of a five-stage soft processor, evaluated on the inner control loop of a reaction-wheel self-balancing bicycle. Starting from a custom 32-bit RISC core in the MIPS tradition—five pipeline stages, full operand forwarding with a single-cycle load-use interlock, and a 33.33 MHz clock on an Artix-7 FPGA—we specialize the design in two ways. First, two frequently accessed peripheral inputs are mapped directly into architectural register state, allowing for continuous updates by hardware. Second, four periodic pulse-width-modulation (PWM) channels are offloaded to hardware, reducing software overhead. Thus, all ten sensor reads in the control loop incur no dedicated instruction cost, which contrasts with the memory-mapped equivalent that requires explicit loads, leading to significantly reduced instruction counts and cycles. We analyze two configurations: the archived one with a worst-case loop of 91 cycles and the integrated one with a loop of 43 cycles. These configurations demonstrate margins of over 7,000× against a 20 ms actuation frame, underscoring the benefits of our design in terms of instruction efficiency and software simplicity. The contribution includes a detailed assessment of the implications of these design choices on performance and operational characteristics.