2026 Broechin Dryas Interconnect Tracing

The proliferation of heterogeneous components in modern computing systems has led to the need for advanced interconnects with higher bandwidth and lower latency. Developing, debugging, and analyzing implementations of these systems, particularly those using FPGA technology, necessitates extensive engineering efforts, especially given the large amounts of trace data produced. In this paper, we introduce Dryas, an open-source tool designed for the analysis of such interconnects, developed with minimal hardware alongside a high-speed, low-latency interconnect implementation. Our runtime reprogrammable overlay engine is capable of inspecting the interconnect for rare and complex events during full operation, utilizing non-deterministic finite automata (NFAs) implemented through state transition elements (STEs) to achieve caching at a granular level. This allows for rapid updates to the filtering criteria without reprogramming the FPGA or disrupting the operational application. We detail the underlying mathematics of the NFAs and their practical implementation on a coherent CPU-FPGA platform. Furthermore, we assess the scalability of Dryas with varying NFA sizes and present its application in debugging interconnect implementations and analyzing cache behaviors.