Brandon P. Hippe, David C. Burnett
Hardware optimization is critical in the design of efficient wireless communication systems. Wireless communication hardware often consumes a significant fraction of the total system’s power budget, with much of this power used in circuits that reduce various types of noise, particularly in the analog front end. The Single-Chip Micro Mote (SCµM) uses a crystal-free radio architecture and makes design trade-offs that favor power consumption over noise performance while maintaining standards compatibility with popular Internet-of-Things (IoT) protocols such as IEEE 802.15.4 and Bluetooth Low Energy. In the continued development of SCµM, we recognize that the digital baseband hardware developed can be more closely optimized with the architecture of the chip. In this paper, we present an extensible Python-based RTL generator that is closely linked to simulation and testing environments. This approach provides flexibility for use on different hardware platforms, such as tape-outs and FPGA implementations, and has promise in AI-assisted design workflows.
@article{6042cf78-823a-4bc2-b065-3a1ca4389a55,
title={2026 Hippe RTL Generator Wireless System},
author={Brandon P. Hippe and David C. Burnett},
year={2026},
language={en}
}TY - JOUR TI - 2026 Hippe RTL Generator Wireless System AU - Brandon P. Hippe AU - David C. Burnett PY - 2026 LA - en ER -
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