A single-precision floating-point systolic Givens-QRD Triangular Solver for MVDR Beamforming

Computation of adaptive beamforming weights in Minimum Variance Distortionless Response (MVDR) processing is a latency-critical operation that poses significant challenges for real-time hardware implementation. This paper presents an FPGA implementation of a systolic Givens-rotation QR decomposition pipeline for MVDR beamforming on a simulated 32-element ultrasound transducer array, using single-precision floating-point arithmetic. The design is deployed on a Zynq UltraScale+ FPGA at 100 MHz with three parallel kernel instances operating concurrently, achieving a measured throughput of 31,123 weight vectors/s at 90.9% parallel efficiency relative to the measured single-instance rate. At an estimated 2.451 W of programmable-logic power, and 5.286 W including the processing system, this corresponds to 12,698 and 5,888 weight vectors/s/W, respectively. Under a matched three-way dispatch, a 24-core Intel Xeon Gold 5220R at 2.20 GHz achieves 465,699 weight vectors/s at a measured 83.08 W package power, corresponding to 5,606 weight vectors/s/W. The FPGA therefore attains 2.3×the power-normalised throughput of the processor on a programmable-logic basis and 1.05×on a total on-chip basis. In contrast, the processor retains a raw throughput advantage of approximately 15×at this operating point. Numerical precision is validated against MATLAB float32 reference outputs from a Field II cyst phantom simulation, achieving a 100% pass rate with a root mean square error of 5.10×10 −7, confirming near-theoretical finite-precision behaviour without systematic bias.